In recent years, an electrostatic capacitor having a high capacitance, high accuracy and a low leakage current has been required in various filter circuits and analog-digital converter circuits incorporated in analog-digital LSI (Large Scale Integrated circuit), transmitting/receiving circuits incorporated in RF (Radio Frequency) transmitting/receiving LSI, and others. Also, increase in the integration of the electrostatic capacitor has also been required for reducing the cost of LSI.
As an electrostatic capacitor of this type, an electrostatic capacitor with a so-called MIM structure in which a capacitance insulating film is disposed between a pair of electrodes (a lower electrode and an upper electrode) made of metal films formed on a semiconductor substrate is known.
For example, IBM Journal Research and Development Vol. 47 No. 23 2/3 Mar./May 2003, pp. 101 to 135 (Non-Patent Document 1) describes a technique in which, after a metal film for a lower electrode, a capacitance insulating film and a metal film for an upper electrode are sequentially deposited on a semiconductor substrate, these films are patterned by the dry etching using a photoresist film as a mask, thereby forming an electrostatic capacitor with a parallel-plate MIM structure.
Japanese Patent Application Laid-Open Publication No. 2008-210996 (Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 2005-142435 (Patent Document 2) describe a manufacturing technique of an electrostatic capacitor in which an opening part is provided in an interlayer insulating film on a lower electrode formed on a semiconductor substrate, and a capacitance insulating film and an upper electrode are formed in this opening part.
The method for manufacturing the electrostatic capacitor described in the Patent Document 1 includes: a step of forming a first metal film (for example, an aluminum alloy film) on a first interlayer insulating film of a semiconductor substrate; a step of forming a first upper-layer barrier film (for example, a stacked film of a titanium film and a titanium nitride film) on the first metal film; a step of processing the first metal film and the stacked film of the first upper-layer barrier film, thereby forming first metal wiring and a lower electrode of the electrostatic capacitor at the same time; a step of forming a second interlayer insulating film covering the first metal wiring and the lower electrode; a step of partially removing the second interlayer insulating film, thereby exposing a part of an upper surface of the first upper-layer barrier film constituting a part of the lower electrode; a step of forming a capacitance insulating film (for example, a silicon nitride film) of the electrostatic capacitor on the exposed first barrier film of the lower electrode; a step of forming a second metal film (for example, an aluminum alloy film) on the second interlayer insulating film and the electrostatic capacitance insulating film; a step of forming a second upper-layer barrier film (for example, a stacked film of a titanium film and a titanium nitride film) on the second metal film; and a step of processing the second metal film and the stacked film of the second upper-layer barrier film, thereby forming second metal wiring and an upper electrode of the electrostatic capacitor at the same time.
The method for manufacturing the electrostatic capacitor described in the Patent Document 2 includes: a step of forming a first electrode (a lower electrode) of the electrostatic capacitor made of a first-layer metal film (for example, a stacked film of a TiN film, an AlCu film and a TiN film) on a surface of an insulating film on a semiconductor substrate; a step of forming a first interlayer insulating film on the first electrode; a step of etching a part of the first interlayer insulating film, thereby forming an opening part from which the surface of the first electrode is exposed; a step of depositing a dielectric film (for example, a silicon nitride film) and a second-layer metal film (for example, a stacked film of an AlCu film and a TiN film) on the first interlayer insulating film including the interior of the opening part; and a step of polishing the second-layer metal film and the dielectric film by a chemical mechanical polishing (CMP) method, thereby forming a dielectric film and a second electrode (an upper electrode) of the electrostatic capacitor in the opening part.
Japanese Patent Application Laid-Open Publication No. 2007-201062 (Patent Document 3) relates to a method for forming an electrostatic capacitor with a MIS (Metal Insulator Silicide) structure and discloses a method in which, after a lower electrode of the electrostatic capacitor made of a metal silicide film (for example, Ni silicide) is formed on a semiconductor substrate, a capacitance insulating film made of, for example, a nitride film and an upper electrode made of a metal film (for example, a Ni film) are formed in a recess part (a recess part whose periphery is surrounded by an oxide film) on the lower electrode.
The above-described electrostatic capacitor is formed at the same time in the step of forming a gate electrode of an N-type MIS transistor having the stacked structure of the metal silicide film, the capacitance insulating film and the metal film. The capacitance insulating film and the upper electrode of the electrostatic capacitor are formed by polishing the capacitance insulating film and the metal film, which are deposited on the oxide film including the interior of the recess part on the lower electrode, by a CMP method, thereby causing the capacitance insulating film and the metal film to remain in the opening part.